`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/22 17:23:16
// Design Name: 
// Module Name: regfile
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module regfile(
    input  logic             clk,

    input  logic             we,
    input  logic [ 4: 0]     radr1,radr2,radr3,radr4,
    input  logic [31: 0]     write_data,

    output logic [31: 0]     read_rs,read_rt,read_rd
    );

    logic [31: 0] register [31: 0]; //32 registers

    always @(negedge clk) begin // change to negedge for the reason that regfile
                                // can read and write in a single cycle.
        if(we) begin
            register[radr4] <= write_data;
        end
    end
    initial begin
        register[0] = 32'b0;
    end
    assign read_rs = register[radr1];
    assign read_rt = register[radr2];
    assign read_rd = register[radr3];

endmodule
